1. Field of the Invention
The invention relates in general to a method of fabricating a memory. More particularly, this invention relates to a method of fabricating a flash memory.
2. Description of the Related Art
A flash memory is a kind of non-volatile memory (NVM) with the characteristics of a small dimension, fast access speed and low power consumption. Since the data erasing is performed in a xe2x80x9cblock by blockxe2x80x9d fashion, the operation speed is faster than other memory.
The basic structure of the flash memory comprises a stacked gate structure assembled by a tunnel oxide layer, a floating gate, a dielectric layer and a control gate, and a source/drain region in the substrate at two sides of the stacked gate structure. In addition, the flash memory further comprises a peripheral circuit memory around the memory circuit region to integrate the peripheral devices for data writing/erasing/reading.
Many flash memories use an intercrossing control gate line and a bit line that connect to the drain region to control the write operation of an individual memory cell, and the source regions at the other side of the control gate are connected to each other. In this kind of flash memory, in order to save the volume occupied by the interconnect structure between the source region, the shallow trench isolations between the gates are removed. An ion implantation step is then performed to form a common source, also referred to as a buried source line. In this method, a self-aligned source (SAS) process is performed. That is, the shallow trench isolation between every other pair of gates has to be removed.
In the conventional fabrication process of a flash memory, the shallow trench isolations in both the memory circuit region and the peripheral circuit region are formed in the same photolithography and etching process. Therefore, the depth and topography for the shallow trench isolations in both regions are the same. A high voltage is typically required for the write/erase operation of a flash memory. Thus, for a process under 0.25 micron, the depth for the shallow trench isolation in the peripheral circuit region that controls the write/erase function has to be deeper than 0.4 microns to provide a sufficient isolation effect.
In the self-aligned source process, as the photoresist layer covering the gates is always narrower than the width of the gate, a portion of the gate is exposed. In order to remove a shallow trench isolation deeper than 0.4 micron, the exposed gate is inevitably damaged. In addition, as the shallow trench isolation is typically formed with an inclined sidewall and a rounded bottom surface to release stress, an isolation structure having a width of about 0.35 micron is required to have a depth larger than 0.4 micron. The above features decrease the integration of the flash memory.
The invention provides a method of fabricating a flash memory. A plurality of first shallow trench isolations is formed in a memory circuit region on a substrate, and a plurality of second shallow trenches is formed in a peripheral circuit region on the substrate. The second shallow trench isolations are deeper than the first shallow trench isolations. A plurality of stacked gates is formed on the substrate in the memory circuit region along a direction perpendicular to the shallow trench isolations. Each stacked gate comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate. The first shallow trench isolations located between every other pair of the stacked gates are removed. A self-aligned source process is performed to form a common source region between every other pair of the stacked gates, while a column of separate drain regions is also formed between every alternate pair of the stacked gates. The drain regions in the same column are separated from each other by the first shallow trench isolations.
The invention further provides a structure of a flash memory. A substrate comprises a memory circuit region and a peripheral circuit region comprises a plurality of second shallow trench isolations. The memory circuit region comprises a plurality of stacked gates, preferably parallel to each other on the substrate. A common source and a column of drain regions are formed in the substrate between every alternate pair of the stacked gates. The drain regions in the same column are separated from each other by a plurality of first shallow trench isolations. The peripheral circuit region comprises a plurality of second shallow trench isolations deeper than the first shallow trench isolations.
As mentioned above, the first shallow trench isolations formed in the memory circuit region are shallower than the shallow trench isolations formed in the peripheral circuit region. Therefore, the damage to the gate during the removal step of the shallow trench isolations in the memory circuit region is minimized, or even prevented. In addition, as the shallow trench isolations formed in the memory circuit region are shallower, the required width is also reduced, so that the integration of the flash memory is increased. The shallow trench isolations formed in the peripheral circuit are maintained at a required depth, so that the operation speed is not affected while the integration is enhanced. Furthermore, as the shallow trench isolations are shallower in the memory circuit region, the common source formed after removing the shallow trench isolation region is formed with a less uneven profile, so that the electrical performance is enhanced.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.